UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 400

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
To transfer data from the TABnCCRm register to the CCRm buffer register, the TABnCCR1 register must be
written.
To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the
TABnCCR0 register, set the active level width to the TABnCCR2 and TABnCCR3 registers, and then set the
active level width to the TABnCCR1 register.
To change only the cycle of the PWM waveform, first set the cycle to the TABnCCR0 register, and then write
the same value to the TABnCCR1 register.
To change only the active level width (duty factor) of the PWM wave, first set the active level to the TABnCCR2
and TABnCCR3 registers, and then set the active level to the TABnCCR1 register.
To change only the active level width (duty factor) of the PWM waveform output by the TOABn1 pin, only the
TABnCCR1 register has to be set.
To change only the active level width (duty factor) of the PWM waveform output by the TOABn2 and TOABn3
pins, first set the active level width to the TABnCCR2 and TABnCCR3 registers, and then write the same value
to the TABnCCR1 register.
After the TABnCCR1 register is written, the value written to the TABnCCRm register is transferred to the CCRm
buffer register in synchronization with the timing of clearing the 16-bit counter, and is used as the value to be
compared with the value of the 16-bit counter.
To write the TABnCCR0 to TABnCCR3 registers again after writing the TABnCCR1 register once, do so after
the INTTABnCC0 signal is generated.
undefined because the timing of transferring data from the TABnCCRm register to the CCRm buffer register
conflicts with writing the TABnCCRm register.
Remark
m = 0 to 3,
n = 0, 1
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Otherwise, the value of the CCRm buffer register may become
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