UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 835

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(7) IIC division clock select registers 0, 1 (OCKS0, OCKS1)
(8) IIC shift registers 0 to 2 (IIC0 to IIC2)
The OCKSm registers control the I
These registers control the I
the OCKS1 register.
These registers can be read or written in 8-bit units.
Reset sets these registers to 00H.
The IICn registers are used for serial transmission/reception (shift operations) synchronized with the serial clock.
These registers can be read or written in 8-bit units, but data should not be written to the IICn registers during a
data transfer.
Access (read/write) the IICn registers only during the wait period. Accessing these registers in communication
states other than the wait period is prohibited. However, for the master device, the IICn registers can be written
once only after the transmission trigger bit (IICCn.STTn bit) has been set to 1.
A wait state is released by writing the IICn registers during the wait period, and data transfer is started (n = 0 to 2).
Reset sets these registers to 00H.
After reset: 00H
(n = 0 to 2)
IICn
OCKSm
(m = 0, 1)
After reset: 00H
7
OCKSTHm
OCKSENm
R/W
0
1
0
0
0
0
1
0
2
C00 division clock via the OCKS0 register and the I
R/W
Stops I
Enables I
OCKSm1
6
0
0
0
1
1
0
2
C0n division clock (n = 0 to 2, m = 0, 1).
2
C division clock operation
Address: OCKS0 FFFFF340H, OCKS1 FFFFF344H
2
C division clock operation
OCKSm0
Address: IIC0 FFFFFD80H, IIC1 FFFFFD90H, IIC2 FFFFFDA0H
5
0
0
1
0
1
0
Operation setting of I
OCKSENm OCKSTHm
f
f
f
f
f
XX
XX
XX
XX
XX
/4
/6
/8
/10
/2
4
Selection of I
3
2
C division clock
2
C division clock
0
2
OCKSm1 OCKSm0
2
C01 and I
1
CHAPTER 19 I
2
C02 division clocks via
Page 835 of 1509
0
2
C BUS