UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 283

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(2) PWM output mode operation timing
(a) Changing pulse width during operation
To change the PWM waveform while the counter is operating, write the TAAnCCR1 register last.
Rewrite the TAAnCCRm register after writing the TAAnCCR1 register after the INTTAAnCC1 signal is detected.
To transfer data from the TAAnCCRm register to the CCRm buffer register, the TAAnCCR1 register must be
written.
To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the
TAAnCCR0 register and then set the active level to the TAAnCCR1 register.
To change only the cycle of the PWM waveform, first set the cycle to the TAAnCCR0 register, and then write
the same value to the TAAnCCR1 register.
To change only the active level width (duty factor) of the PWM waveform, only the TAAnCCR1 register has to
be set.
After data is written to the TAAnCCR1 register, the value written to the TAAnCCRm register is transferred to the
CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared
with the 16-bit counter.
To write the TAAnCCR0 or TAAnCCR1 register again after writing the TAAnCCR1 register once, do so after the
INTTAAnCC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined
because the timing of transferring data from the TAAnCCRm register to the CCRm buffer register conflicts with
writing the TAAnCCRm register.
Remark
CCR0 buffer register
CCR1 buffer register
INTTAAnCC0 signal
TAAnCCR0 register
TAAnCCR1 register
TOAAn1 pin output
16-bit counter
TAAnCE bit
n = 0 to 3, 5
m = 0, 1
FFFFH
0000H
D
10
D
D
00
00
D
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
10
D
D
D
10
10
D
00
00
D
10
D
00
D
D
11
01
D
01
D
11
D
D
D
11
01
11
D
01
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