UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 942

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(1) CAN0 global control register (C0GMCTRL)
(a) Read
(b) Write
(a) Read
Remark When the CAN sleep mode/CAN stop mode is entered, or when the GOM bit is cleared to 0, the
The C0GMCTRL register is used to control the operation of the CAN module.
Cautions 1. While the MBON bit is cleared (to 0), software access to the message buffers
After reset: 0000H
C0GMCTRL
C0GMCTRL
MBON
0
1
Write access and read access to the message buffer register and the transmit/receive history list registers is
disabled.
Write access and read access to the message buffer register and the transmit/receive history list registers is
enabled.
MBON bit is cleared to 0. When the CAN sleep mode/CAN stop mode is released, or when the GOM
bit is set to 1, the MBON bit is set to 1.
2. This bit is read-only. Even if 1 is written to the MBON bit while it is 0, the value of the
(C0MDATA0m, C0MDATA1m, C0MDATA01m, C0MDATA2m, C0MDATA3m, C0MDATA23m,
C0MDATA4m, C0MDATA5m, C0MDATA45m, C0MDATA6m, C0MDATA7m, C0MDATA67m,
C0MDLCm, C0MCONFm, C0MIDLm, C0MIDHm, and C0MCTRLm), or registers related to
transmit history or receive history (C0LOPT, C0TGPT, C0LIPT, and C0RGPT) is disabled.
MBON bit does not change, and access to the message buffer registers, or registers
related to transmit history or receive history remains disabled.
MBON
15
15
7
0
7
0
0
R/W
Bit enabling access to message buffer register, transmit/receive history registers
Address:
14
14
0
6
0
0
6
0
03FEC000H
13
13
0
5
0
0
5
0
12
12
0
4
0
0
4
0
11
11
0
3
0
0
3
0
CHAPTER 20 CAN CONTROLLER
10
10
0
2
0
0
2
0
EFSD
EFSD
Set
9
0
1
9
1
0
Page 942 of 1509
GOM
GOM
Clear
GOM
Set
8
0
0
8
0
(1/2)