UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 251

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
each time the valid edge of external event count input is detected. Additionally, the set value of the TAAnCCR0 register is
transferred to the CCR0 buffer register.
to 0000H, and a compare match interrupt request signal (INTTAAnCC0) is generated.
value of TAAnCCR0 register + 1) times.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
When the TAAnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
The INTTAAnCC0 signal is generated each time the valid edge of the external event count input has been detected (set
TAAnCTL1
TAAnCTL0
TAAnIOC0
TAAnIOC2
(a) TAAn control register 0 (TAAnCTL0)
(b) TAAn control register 1 (TAAnCTL1)
(c) TAAn I/O control register 0 (TAAnIOC0)
(d) TAAn I/O control register 2 (TAAnIOC2)
TAAnCE
0/1
0
0
0
Figure 7-16. Register Setting for Operation in External Event Count Mode (1/2)
TAAnEST
0
0
0
0
TAAnEEE
0
0
0
0
0
0
0
0
TAAnEES1
TAAnOL1
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
0/1
0
0
0
TAAnOE1 TAAnOL0 TAAnOE0
TAAnEES0 TAAnETS1 TAAnETS0
TAAnCKS2 TAAnCKS1 TAAnCKS0
TAAnMD2 TAAnMD1 TAAnMD0
0/1
0
0
0
0
0
0
0
0
0
1
0
0: Disables TOAAn0 pin output
0: Disables TOAAn1 pin output
Select valid edge of
external event count input
0, 0, 1:
External event count mode
0: Stops counting
1: Enables counting
Page 251 of 1509