UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 57

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
3.2.2
system register numbers listed below.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
The system registers control the status of the CPU and hold interrupt information.
These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the
Notes 1. Because only one set of these registers is available, the contents of these registers must be saved by
Caution Even if EIPC or FEPC, or bit 0 of CTPC is set to 1 by the LDSR instruction, bit 0 is ignored when
Remark
Register
Number
21 to 31
System
6 to 15
16
17
18
19
20
0
1
2
3
4
5
System register set
2. These registers can be accessed only during the interval between the execution of the DBTRAP instruction
program if multiple interrupts are enabled.
or illegal opcode and DBRET instruction execution.
execution is returned to the main routine by the RETI instruction after interrupt servicing (this is
because bit 0 of the PC is fixed to 0). Set an even value to EIPC, FEPC, and CTPC (bit 0 = 0).
√: Can be accessed
×: Access prohibited
Interrupt status saving register (EIPC)
Interrupt status saving register (EIPSW)
NMI status saving register (FEPC)
NMI status saving register (FEPSW)
Interrupt source register (ECR)
Program status word (PSW)
Reserved for future function expansion (operation is not guaranteed if these
registers are accessed)
CALLT execution status saving register (CTPC)
CALLT execution status saving register (CTPSW)
Exception/debug trap status saving register (DBPC)
Exception/debug trap status saving register (DBPSW)
CALLT base pointer (CTBP)
Reserved for future function expansion (operation is not guaranteed if these
registers are accessed)
System Register Name
Table 3-2. System Register Numbers
Note 1
Note 1
Note 1
Note 1
CHAPTER 3 CPU FUNCTION
LDSR Instruction STSR Instruction
√
√
Operand Specification
Note 2
Note 2
√
√
√
√
×
√
×
√
√
√
×
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√
√
Note 2
Note 2
√
√
√
√
√
√
×
√
√
√
×