UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 321

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
7.7.1
TAA0 is used as the slave timer.
master timer is set to 1. The slave timer operates by the count clock supplied from the master timer (TAA1). After the
slave timer starts operating, however, the 16-bit counter of the slave timer (TAA0) is not cleared even if the 16-bit counter
of the master timer (TAA1) is cleared to 0000H upon a match between the 16-bit counter value of the master timer (TAA1)
and the TAA1CCR0 register value, because each timer operates individually.
register of the slave timer is not affected.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
In this section, the operation of the simultaneous-start function is shown, where TAA1 is used as the master timer and
The master timer (TAA1) and slave timer (TAA0) start operating at the same time when the TAA1CTL0.TAA0CE bit of
In the same manner, if the compare register value of the master timer (TAA1) is rewritten by batch writing, the compare
[Initial settings]
[Starting counting]
[End condition]
PWM output mode (simultaneous-start operation)
Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled)
Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled)
[Initial settings of master timer (TAA1)]
[Initial settings of slave timer (TAA0)]
Remark
<1> Set TAA1CTL0.TAA1CE of the master timer to 1.
<2> Start counting.
<3> Changing the setting of the register during operation
• Set TAA1CTL0.TAA0CE of the master timer to 0.
• TAA1CTL1.TAA1MD2 to TAA1CTL1.TAA1MD0 = 100 (setting of PMW output mode)
• TAA1CTL1.TAA1CKS2 to TAA1CTL1.TAA1CKS0 (setting of count clock (any))
• TAA1CCR1, TAA1CCR0 (specification of valid edge of capture trigger)
• TAA1IOC0 (specification of valid edge of capture trigger)
• TAA0CTL1.TAA0SYE = 1, TAA0SYM = 1 (simultaneous-start operation)
• TAA0CTL1.TAA0MD2 to TAA0CTL1.TAA0MD0 = 100 (setting of PMW output mode)
• TAA0CCR0, TAA1CCR1 (specification of valid edge of capture trigger)
• TAA0IOC0 (specification of valid edge of capture trigger)
• The compare register can be rewritten (anytime write).
The initial settings of the master timer and slave timer may be performed in any order.
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
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