UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1166

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
21.6.6 Bridge register
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(1) Bridge interrupt control register (BRGINTT)
11
10
9
8
2
1
0
Bit position
After reset: 0000H
BRGINTT
The BRGINTT register controls the DMA transfer status of the interrupt generate status, and each end point (EP1
to EP4) from EPC to bridge circuit.
The BRGINTT register can be read or written in 16-bit units.
EP4INT
EP3NT
EP2NT
EP1NT
EPCINT2B
EPCINT1B
EPCINT0B
15
0
7
0
Bit name
R/W
Address: 00200400H
14
0
6
0
In EP4, when the DMA transfer is normal terminate, or the error finished in the DMA
transferring, this bit is setting. Clearing to “0” by writing “1”.
In EP3, when the DMA transfer is normal terminate, or the error finished in the DMA
transferring, this bit is setting. Clearing to “0” by writing “1”.
In EP2, when the DMA transfer is normal terminate, or the error finished in the DMA
transferring, this bit is setting. Clearing to “0” by writing “1”.
In EP1, when the DMA transfer is normal terminate, or the error finished in the DMA
transferring, this bit is setting. Clearing to “0” by writing “1”.
Showing the status of the interrupt signal “EPC_INT2B” from EPC.
Clear controlling from the request of EPC register
Showing the status of the interrupt signal “EPC_INT1B” from EPC.
Clear controlling from the request of EPC register
Showing the status of the interrupt signal ”EPC_INT0B” from EPC.
Clear controlling from the request of EPC register
0: DMA transfer not completion
1: DMA transfer completion
0: DMA transfer not completion
1: DMA transfer completion
0: DMA transfer not completion
1: DMA transfer completion
0: DMA transfer not completion
1: DMA transfer completion
0: Interrupt not issued
1: Interrupt issued
0: Interrupt not issued
1: Interrupt issued
0: Interrupt not issued
1: Interrupt issued
13
0
5
0
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
12
0
4
0
EP4INT
11
Function
3
0
EPCINT2B
EP3INT
10
2
EPCINT1B
EP2INT
9
1
EPCINT0B
Page 1166 of 1509
EP1INT
8
0