UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1318

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Notes 1. To lower the power consumption, stop the A/D converter, D/A converter, and USB function controller before
Item
Main clock oscillator (f
Subclock oscillator (f
Internal oscillator (f
PLL
CPU
DMA controller
Interrupt controller
Timer
Real-time counter (RTC)
Watchdog timer (WDT2)
Serial interface
A/D converter
D/A converter
Real-time output function (RTO)
Key interrupt function (KR)
CRC operation circuit
External bus interface
Port function
Internal data
CAN
USB function
Note 2
2.
shifting to the IDLE2 mode.
μ
PD70F3770, 70F3771 only
Setting of IDLE2 Mode
R
TAA0 to TAA5
TAB0, TAB1
TMM0 to TMM3
TMT0
CSIF0 to CSIF4
I
UARTC0 to UARTC4
)
2
XT
C00 to I
X
)
)
2
C02
Table 25-7. Operating Status in IDLE2 Mode
Oscillation enabled
Oscillation enabled
Stops operation
Stops operation
Stops operation
Stops operation
Stops operation
Stops operation
Operable when f
count clock
Stops operation
Operable when f
selected as the count clock
Operable when f
clock
Operable when the SCKFn input clock is selected as the count clock (n = 0 to 4)
Stops operation
Stops operation (but UARTC0 is operable when the ASCKC0 input clock is selected)
Holds operation (conversion result held)
Holds operation (output held
Stops operation (output held)
Operable
Stops operation
See CHAPTER 5 BUS CONTROL FUNCTION.
Retains status before IDLE2 mode was set
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the IDLE2 mode was set.
Stops operation
Operable when the UCLK input is selected as the operation clock or when the PLL is
operating.
When Subclock Is Not Used
Note 1
R
X
R
/8 is selected as the
(divided BRG) is
is selected as the count
−
Note 1
)
Operating Status
Note 1
CHAPTER 25 STANDBY FUNCTION
Oscillation enabled
Operable when f
the count clock
Operable
Operable when f
count clock
When Subclock Is Used
R
R
/8 or f
or f
XT
XT
is selected as the
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is selected as