UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 337

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UPD70F3771GF-GAT-AX

Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet

Specifications of UPD70F3771GF-GAT-AX

Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(3) TABn I/O control register 0 (TABnIOC0)
The TABnIOC0 register is an 8-bit register that controls the timer output (TOABn0 to TOABn3 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TABnIOC0
(n = 0, 1)
After reset: 00H
Note The output level of the timer output pin (TOABnm) specified by the
Cautions 1. Rewrite the TABnOLm and TABnOEm bits when the
Remark
TABnOEm
TABnOLm
TABnOL3
0
1
0
1
7
TABnOLm bit is shown below.
• When TABnOLm bit = 0
Timer output disabled
• When TABnOLm bit = 0: Low level is output from the TOABnm pin
• When TABnOLm bit = 1: High level is output from the TOABnm pin
TOABnm output pin
2. Even if the TABnOLm bit is manipulated when the TABnCE
TABnOE3 TABnOL2 TABnOE2 TABnOL1 TABnOE1 TABnOL0 TABnOE0
Timer output enabled (a square wave is output from the TOABnm pin).
m = 0 to 3
R/W
TOABnm pin high level start
TOABnm pin low level start
6
TABnCTL0.TABnCE bit = 0. (The same value can be written
when the TABnCE bit = 1.)
performed, clear the TABnCE bit to 0 and then set the bits
again.
and TABnOEm bits are 0, the TOABnm pin output level varies.
16-bit counter
TABnCE bit
Address: TAB0IOC0 FFFFF542H, TAB1IOC0 FFFFF562H
TOABnm pin output level setting (m = 0 to 3)
5
TOABnm pin output setting (m = 0 to 3)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
4
3
• When TABnOLm bit = 1
TOABnm output pin
If rewriting was mistakenly
16-bit counter
2
TABnCE bit
Note
1
0
Page 337 of 1509

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