UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 778

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(2) Operation timing
INTCFnR signal
Remark
CFnTSF bit
SCKFn pin
SOFn pin
(1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write C1H to the CFnCTL0 register, and select the transmission mode and MSB first at the same time
(4) Set the CFnSTR.CFnTSF bit to 1 by writing the transmit data to the CFnTX register, and start
(5) When transmission is started, output the serial clock to the SCKFn pin, and output the transmit data
(6) When transmission of the transfer data length set with the CFnCTL2 register is completiond, stop the
(7) To continue transmission, start the next transmission by writing the transmit data to the CFnTX register
(8) To end transmission, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnTXE bit = 0.
f
as enabling the operation of the communication clock (f
transmission.
from the SOFn pin in synchronization with the serial clock.
serial clock output and transmit data output, generate the reception completion interrupt request signal
(INTCFnR) at the last edge of the serial clock, and clear the CFnTSF bit to 0.
again after the INTCFnR signal is generated.
XX
n = 0 to 4
(1)
(2)
(3)
/2 or f
(4)
XX
/3, and master mode.
(5)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
Bit 2
Bit 1
(6)
Bit 0
(7)
CCLK
Bit 7 Bit 6
).
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
Page 778 of 1509
(8)
CCLK
) =