UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 176

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
4.5.3
high level is input to the DRST pin at this time, the on-chip debug mode is set, and the DCK, DMS, DDI, and DDO pins can
be used.
action is taken.
Handle the P56 pin with the utmost care.
4.5.4
down resistor is connected. The pull-down resistor is disconnected when the OCDM0 bit is cleared (0).
4.5.5
4.5.6
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins.
After reset by the RESET pin, the P56/INTP05/DRST pin is initialized to function as an on-chip debug pin (DRST). If a
The following action must be taken if on-chip debugging is not used.
• Clear the OCDM0 bit of the OCDM register (special register) (0)
At this time, fix the P56/INTP05/DRST pin to low level from when reset by the RESET pin is released until the above
If a high level is input to the DRST pin before the above action is taken, it may cause a malfunction (CPU deadlock).
Caution After reset by the WDT2RES signal, clock monitor (CLM), or low-voltage detector (LVI), the
The P56/INTP05/DRST pin has an internal pull-down resistor (30 kΩ TYP.). After a reset by the RESET pin, a pull-
When the power is turned on, the following pins may output an undefined level temporarily even during reset.
• P10/ANO0 pin
• P11/ANO1 pin
• P53/SIF2/TIAB00/KR3/TOAB00/RTP03/DDO pin (V850ES/JG3-H only)
In port mode, the following port pins do not have hysteresis characteristics.
P00 to P05
P20 to P25
P30 to P37
P40 to P42
P50 to P56
P60 to P65
P90 to P915
Cautions on on-chip debug pins (V850ES/JG3-H only)
Cautions on P56/INTP05/DRST pin
Cautions on P10, P11, and P53 pins when power is turned on
Hysteresis characteristics
P56/INTP05/DRST pin is not initialized to function as an on-chip debug pin (DRST). The OCDM
register holds the current value.
CHAPTER 4 PORT FUNCTIONS
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