UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 780

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(2) Operation timing
SIFn pin capture
INTCFnR signal
CFnTSF bit
SCKFn pin
SIFn pin
(1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write A1H to the CFnCTL0 register, and select the reception mode and MSB first at the same time as
(4) Set the CFnSTR.CFnTSF bit to 1 by performing a dummy read of the CFnRX register, and start
(5) When reception is started, output the serial clock to the SCKFn pin, and capture the receive data of the
(6) When reception of the transfer data length set with the CFnCTL2 register is completed, stop the serial
(7) To continue reception, read the CFnRX register while keeping the CFnCTL0.CFnSCE bit = 1 after the
(8) To read the CFnRX register without starting the next reception, write the CFnSCE bit = 0.
(9) Read the CFnRX register.
(10) To end reception, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnRXE bit = 0.
Remark
timing
f
enabling the operation of the communication clock (f
reception.
SIFn pin in synchronization with the serial clock.
clock output and data capturing, generate the reception completion interrupt request signal (INTCFnR)
at the last edge of the serial clock, and clear the CFnTSF bit to 0.
INTCFnR signal is generated.
XX
/2 or f
(1)
(2)
(3)
n = 0 to 4
(4)
XX
/3, and master mode.
(5)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
Bit 2
Bit 1
(6)
Bit 0
(7)
CCLK
).
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(8)
(9)
Page 780 of 1509
(10)
CCLK
) =