UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 475

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(c) Notes on rewriting TT0CCR0 register
If the value of the TT0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow. When an overflow may occur, stop counting and then change the set value.
If the value of the TT0CCR0 register is changed from D
than D
rewritten. Consequently, the value of the 16-bit counter that is compared is D
Because the count value has already exceeded D
and then counts up again from 0000H. When the count value matches D
and the output of the TOT00 pin is inverted.
Therefore, the INTTT0CC0 signal may not be generated at the interval time “(D
“(D
× Count clock cycle”.
Remark
2
+ 1) × Count clock cycle” as originally expected, but may be generated at an interval of “(10000H + D
1
, the count value is transferred to the CCR0 buffer register as soon as the TT0CCR0 register has been
INTTT0CC0 signal
TT0CCR0 register
TOT00 pin output
Interval time (1):
Interval time (NG): (10000H + D
Interval time (2):
16-bit counter
TT0OL0 bit
TT0CE bit
FFFFH
0000H
L
(D
(D
Interval time (1)
1
2
+ 1) × Count clock cycle
+ 1) × Count clock cycle
D
1
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
D
2
1
+ 1) × Count clock cycle
2
, however, the 16-bit counter counts up to FFFFH, overflows,
D
2
Interval time (NG)
1
D
to D
1
2
while the count value is greater than D
D
2
D
2
, the INTTT0CC0 signal is generated
2
Interval
time (2)
2
.
D
2
1
+ 1) × Count clock cycle” or
Page 475 of 1509
2
but less
2
+ 1)