UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 205

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(a) Example of setting main clock operation → subclock operation
Remark
<1> CK3 bit ← 1:
<2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the following
<3> MCK bit ← 1:
Remark Internal system clock (f
[Description example]
<1> _SET_SUB_RUN :
<2> _CHECK_CLS :
<3> _STOP_MAIN_CLOCK :
Cautions 1. When stopping the main clock, stop the PLL. Also stop the operations of the on-chip
_DMA_DISABLE:
clrl
st.b
set1
tst1
bz
st.b
set1
_DMA_ENABLE:
setl
2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the
The description above is simply an example. Note that in <2> above, the CLS bit is read in a closed
loop.
peripheral functions operating with the main clock.
conditions are satisfied, then change to the subclock operation mode.
Internal system clock (f
0, DCHCn[r0]
r0, PRCMD[r0]
3, PCC[r0]
4, PCC[r0]
_CHECK_CLS
r0, PRCMD[r0]
6, PCC[r0]
0, DCHCn[r0]
Use of a bit manipulation instruction is recommended. Do not change the CK2 to
CK0 bits.
time after the CK3 bit is set until subclock operation is started.
Set the MCK bit to 1 only when stopping the main clock.
Max.: 1/f
CLK
): Clock generated from the main clock (f
bits
XT
(1/subclock frequency)
CLK
) > Subclock (f
-- DMA operation disabled. n = 0 to 3
-- CK3 bit ← 1
-- Wait until subclock operation starts.
-- MCK bit ← 1, main clock is stopped.
-- DMA operation enabled. n = 0 to 3
CHAPTER 6 CLOCK GENERATION FUNCTION
XT
: 32.768 kHz) × 4
XX
) by setting the CK2 to CK0
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