UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 443

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Cautions 1. The TT0ECC bit is valid only in the encoder compare mode. In any other
TT0UDS1
0
0
1
1
TT0UDS0
2. The TT0LDE bit is valid only when the TT0ECM1 and TT0ECM0 bits = 00,
3. The edge detection of the TENC00 and TENC01 inputs specified by the
4. Set the TT0LDE, TT0ECM1, TT0ECM0, TT0UDS1, and TT0UDS0 bits when
5. Be sure to set bits 5 and 6 to “0”.
0
1
0
1
mode, writing “1” to this bit is ignored.
If the TT0CTL0.TT0CE bit is cleared to 0 while the TT0ECC bit = 1, the
values of the timer/counter and capture registers (TT0CCR0 and
TT0CCR1), and the TT0OPT1, TT0EUF, TT0EOF, and TT0ESF flags are
retained.
If the TT0CE bit is set from 0 to 1 when the TT0ECC bit = 1, the value of the
TT0TCW register is not transferred to the 16-bit counter.
01. Writing “1” to this bit is ignored when the TT0ECM1 and TT0ECM0 bits
= 10, 11.
TT0IOC3.TT0EIS1 and TT0IOC3.TT0EIS0 bits is invalid and fixed to both
the rising and falling edges when the TT0UDS1 and TT0UDS0 bits = 10, 11.
the TT0CTL0.TT0CE bit = 0 (the same value can be written to these bits
when the TT0CE bit = 1). If the value of these bits is changed when the
TT0CE bit = 1, the operation cannot be guaranteed. If it is changed by
mistake, clear the TT0CE bit and then set the correct value.
When valid edge of TENC00 input is detected
Counts down when TENC01 = high level.
Counts up when TENC01 = low level.
Counts up when valid edge of TENC00 input is detected.
Counts down when valid edge of TENC01 input is detected.
Counts down when rising edge of TENC00 input is detected.
Counts up when falling edge of TENC00 input is detected.
However, count operation is performed only when
TENC01 = low level.
Both rising and falling edges of TENC00 and TENC01 are
detected. Count operation is automatically identified by
combination of edge detection and level detection.
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Up/down count selection
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