UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 225

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(7) TAAn option register 0 (TAAnOPT0)
The TAAnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
(n = 0 to 3, 5)
TAAnOPT0
After reset: 00H
Cautions 1. Rewrite the TAAnCCS1 and TAAnCCS0 bits when the
TAAnCCS1
TAAnCCS0
The TAAnCCS1 bit setting is valid only in the free-running timer mode.
The TAAnCCS0 bit setting is valid only in the free-running timer mode.
Set (1)
Reset (0)
• The TAAnOVF bit is set to 1 when the 16-bit counter count value overflows from
• An interrupt request signal (INTTAAnOV) is generated at the same time that the
• The TAAnOVF bit is not cleared even when the TAAnOVF bit or the TAAnOPT0
• The TAAnOVF bit can be both read and written, but the TAAnOVF bit cannot be
FFFFH to 0000H in the free-running timer mode or the pulse width measurement
mode.
TAAnOVF bit is set to 1. The INTTAAnOV signal is not generated in modes other
than the free-running timer mode and the pulse width measurement mode.
register are read when the TAAnOVF bit = 1.
set to 1 by software. Writing 1 has no influence on the operation of TAAn.
0
1
0
1
7
0
TAAnOVF
2. Be sure to set bits 1 to 3, 6, and 7 to “0”.
Compare register selected
Capture register selected
Compare register selected
Capture register selected
R/W
TAAnCE bit = 0. (The same value can be written when the
TAAnCE bit = 1.) If rewriting was mistakenly performed,
clear the TAAnCE bit to 0 and then set the bits again.
6
0
Address:
TAAnCCS1TAAnCCS0
Overflow occurred
0 written to TAAnOVF bit or TAAnCTL0.TAAnCE bit = 0
TAAnCCR1 register capture/compare selection
TAAnCCR0 register capture/compare selection
5
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
TAA0OPT0 FFFFF635H, TAA1OPT0 FFFFF645H,
TAA2OPT0 FFFFF655H, TAA3OPT0 FFFFF665H,
TAA5OPT0 FFFFF685H
TAAn overflow detection flag
4
3
0
2
0
1
0
TAAnOVF
0
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