UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 318

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
7.6.2
Table 7-7. This section presents an example of a timer-tuned operation with TAB0 and TAA5.
TAB0CCR2, and TAB0CCR3 registers of the master timer (TAB0) and the TAA5CCR0 and TAA5CCR1 registers of the
slave timer (TAA5) are used as compare registers for duty.
registers of the master and slave timers are rewritten or the same value is written to them when an interrupt, which is
generated if the value of the TAB0CCR0 register of the master timer (TAB0) matches the value of the timer counter, is
generated.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
This section explains the PWM output mode of timer-tuned operation. For combinations of timer-tuned operations, see
The TAB0CCR0 register of the master timer (TAB0) is used as a compare register for cycle, and the TAB0CCR1,
The compare registers can be rewritten during operation and the rewriting method is batch writing.
Batch writing is enabled when the TAB0CCR1 register of the master timer (TAB0) is written, and all the compare
(1) Settings in PWM output mode
[Initials setting]
[Starting counting]
[End condition]
PWM output mode (during timer-tuned operation)
Master timer: TAB0CTL0.TAB0CE = 0 (operation disabled)
Slave timer: TAA5CTL0.TAA5CE = 0 (operation disabled)
[Initial settings of master timer (TAB0)]
[Initial settings of slave timer (TAA5)]
Remark
<1> Set TAB0CTL0.TAB0CE of the master timer to 1.
<2> Start counting.
<3> Changing the setting of the register during operation
• Set TAB0CTL0.TAB0CE of the master timer to 0.
• TAB0CTL1.TAB0MD2 to TAB0CTL1.TAB0MD0 = 100 (setting of PWM output mode)
• TAB0OPT0.TAB0CCS3 to TAB0OPT0.TAB0CCS0 = 0000 (setting of capture/compare select bit to
• TAB0CCR0, TAB0CCR1, TAB0CCR2, and TAB0CCR3 registers are set.
• TAA5CTL1.TAA5SYE = 1 (setting of timer-tuned operation)
• TAA5CTL1.TAA5MD2 to TAA5CTL1.TAA5MD0 = 101 (setting of free-running timer mode)
• TAA5OPT0.TAA5CCS1 and TAA5OPT0.TAA5CCS0 = 00 (setting of capture/compare select bit to
• TAA5CCR0 and TAA5CCR1 registers are set.
“compare”.)
“compare”.)
• The compare register can be rewritten (batch rewrite).
The initial settings of the master timer and slave timer may be performed in any order.
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Page 318 of 1509