UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 490

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOT01
pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted. (The
output of the TOT00 pin is inverted. The TOT01 pin outputs a high level regardless of the status (high/low) when a trigger
occurs.)
value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match
interrupt request signal (INTTT0CC1) is generated when the count value of the 16-bit counter matches the value of the
CCR1 buffer register.
counter matches the value of the CCRn buffer register and the 16-bit counter is cleared to 0000H.
as the trigger (n = 0, 1).
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
16-bit timer/event counter T waits for a trigger when the TT0CE bit is set to 1. When the trigger is generated, the 16-bit
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The compare match request signal (INTTT0CC0) is generated the next time the 16-bit counter counts after its count
The value set to the TT0CCRn register is transferred to the CCRn buffer register when the count value of the 16-bit
The valid edge of an external trigger input (EVTT0), or setting the software trigger (TT0CTL1.TT0EST bit) to 1 is used
External trigger input
Active level width = (Set value of TT0CCR1 register) × Count clock cycle
Cycle = (Set value of TT0CCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TT0CCR1 register)/(Set value of TT0CCR0 register + 1)
INTTT0CC0 signal
INTTT0CC1 signal
TT0CCR0 register
TT0CCR1 register
(EVTT0 pin input)
TOT00 pin output
TOT01 pin output
16-bit counter
TT0CE bit
FFFFH
0000H
Figure 9-22. Basic Timing in External Trigger Pulse Output Mode
trigger
Wait
for
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)
Active level
width (D
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Cycle (D
D
1
1
)
D
0
0
+ 1)
D
D
0
1
D
1
D
0
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)
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