UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1389

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UPD70F3771GF-GAT-AX

Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet

Specifications of UPD70F3771GF-GAT-AX

Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
V850ES/JG3-H, V850ES/JH3-H
32.1 Debugging with DCU
debug emulator (MINICUBE).
32.1.1 Connection circuit example
32.1.2 Interface signals
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Programs can be debugged using the debug interface pins (DRST, DCK, DMS, DDI, and DDO) to connect the on-chip
Notes 1. Example of pin connection when MINICUBE is not connected
The interface signals are described below.
(1) DRST
Figure 32-1. Circuit Connection Example When Debug Interface Pins Are Used for Communication Interface
This is a reset input signal for the on-chip debug unit. It is a negative-logic signal that asynchronously initializes
the debug control unit.
MINICUBE raises the DRST signal when it detects V
and starts the on-chip debug unit of the device.
When the DRST signal goes high, a reset signal is also generated in the CPU.
When starting debugging by starting the integrated debugger, a CPU reset is always generated.
2. A pull-down resistor is provided on chip.
3. For flash memory rewriting
MINICUBE
RESET
FLMD0
DRST
DMS
DDO
GND
VDD
DCK
DDI
Note 1
DD
of the target system after the integrated debugger is started,
CHAPTER 32 ON-CHIP DEBUG FUNCTION
EV
DCK
DMS
DDI
DDO
DRST
RESET
FLMD0
FLMD1/PDL5
V
SS
V850ES/JG3-H,
V850ES/JH3-H
DD
Note 2
Note 3
Page 1389 of 1509

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