UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 832

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
After reset: 00H
(n = 0 to 2)
(4) IIC clock select registers 0 to 2 (IICCL0 to IICCL2)
IICCLn
The IICCLn registers set the transfer clock for I
These registers can be read or written in 8-bit or 1-bit units. However, the CLDn and DADn bits are read-only.
Set the IICCLn registers when the IICCn.IICEn bit = 0.
The SMCn, CLn1, and CLn0 bits are set by combining the IICXn.CLXn bit and the OCKSTHm, OCKSm1, and
OCKSm0 bits of the OCKSm register (see 19.4 (6) I
Reset sets these registers to 00H.
Note Bits 4 and 5 are read-only bits.
Caution Be sure to clear bits 7 and 6 to “0”.
Remark
Condition for clearing (CLDn bit = 0)
• When the SCL0n pin is at low level
• When the IICEn bit = 0 (operation stop)
• After reset
Condition for clearing (DADn bit = 0)
• When the SDA0n pin is at low level
• When the IICEn bit = 0 (operation stop)
• After reset
The digital filter can be used only in high-speed mode.
In high-speed mode, the transfer clock does not vary according to the DFCn bit setting (on/off).
The digital filter is used to eliminate noise in high-speed mode.
SMCn
CLDn
DADn
DFCn
0
1
7
0
0
1
0
1
0
1
When the IICCn.IICEn bit = 0, 0 is read when reading the CLDn and DADn bits.
R/W
The SCL0n pin was detected at low level.
The SCL0n pin was detected at high level.
The SDA0n pin was detected at low level.
The SDA0n pin was detected at high level.
Operation in standard mode.
Operation in high-speed mode.
Digital filter off.
Digital filter on.
Note
6
0
CLDn
<5>
Address: IICCL0 FFFFFD84H, IICCL1 FFFFFD94H, IICCL2 FFFFFDA4H
Detection of SCL0n pin level (valid only when IICCn.IICEn bit = 1)
Detection of SDA0n pin level (valid only when IICEn bit = 1)
DADn
<4>
2
C0n.
Digital filter operation control
Operation mode switching
2
C0n transfer clock setting method) (n = 0 to 2, m = 0, 1).
SMCn
3
Condition for setting (CLDn bit = 1)
• When the SCL0n pin is at high level
Condition for setting (DAD0n bit = 1)
• When the SDA0n pin is at high level
DFCn
2
CLn1
1
CLn0
CHAPTER 19 I
0
Page 832 of 1509
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C BUS