UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 642

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(3) Real-time counter control register 2 (RC1CC2)
The RC1CC2 register is an 8-bit register that controls the alarm interrupt function and waiting of counters.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Cautions 1. See 12.4.5 Changing INTRTC1 interrupt setting during the real-time counter operation
RC1CC2
2. Confirm that the RWST bit is set to 1 when reading or writing each counter value.
3. The RWST bit does not become 0 while each counter is being written, even if the RWAIT
After reset: 00H
when rewriting the WALE bit while the real-time counter operates (RC1PWR bit = 1).
bit is set to 0. It becomes 0 when writing to each counter is completed.
This is a status flag indicating whether the RWAIT bit setting is valid.
Read or write counter values after confirming that the RWST bit is 1.
This bit controls the operation of the counters.
Be sure to write 1 to this bit when reading or writing counter values.
If the RC1SUBC register overflows while the RWAIT bit is 1, the overflow
information is retained internally and the RC1SEC register is counted up after two
clocks or less after 0 is written to the RWAIT bit.
However, if the second counter value is rewritten while the RWAIT bit is 1, the
retained overflow information is discarded.
RWAIT
WALE
RWST
WALE
7
0
1
0
1
0
1
Does not generate interrupt upon alarm match.
Generates interrupt upon alarm match.
Counter operating
Counting up of second to year counters stopped
(Reading and writing of counter values enabled)
Sets counter operation.
Stops count operation of second to year counters.
(Counter value read/write mode)
R/W
6
0
Address: FFFFFADFH
5
0
Alarm interrupt (INTRTC1) operation control
Real-time counter wait control
Real-time counter wait state
4
0
3
0
CHAPTER 12 REAL-TIME COUNTER
2
0
RWST
1
RWAIT
0
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