UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1428

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
(T
Remarks 1. T = 1/f
Bus Hold (CLKOUT Asynchronous)
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
HLDRQ high-level width
HLDAK low-level width
Delay time from HLDAK↑ to bus output t
Delay time from HLDRQ↓ to HLDAK↓
Delay time from HLDRQ↑ to HLDAK↑
Delay time from bus float to HLDAK↓
A
Address bus (output)
(2) During bus hold (V850ES/JH3-H only)
WR0, WR1 (output)
= −40 to +85°C, V
CLKOUT (output)
HLDAK (output)
(a) CLKOUT asynchronous
HLDRQ (input)
CS0, CS2,
CS3 (output)
ASTB (output)
Data bus (I/O)
RD (output),
2. n: Number of wait clocks inserted in the bus cycle
3. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
The sampling timing changes when a programmable wait is inserted.
Parameter
CPU
DD
(f
= EV
CPU
: CPU operating clock frequency)
DD
= UV
DD
t
t
t
t
t
WHQH
WHAL
DHAC
DHQHA1
DHQHA2
DFHA
= AV
Symbol
REF0
<44>
<45>
<46>
<47>
<48>
<49>
<47>
= AV
TI
Conditions
REF1
<49>
, V
SS
TH
= AV
T + 16
T − 10
−7
2.5T
0.5T + 17
0
CHAPTER 33 ELECTRICAL SPECIFICATIONS
SS
= 0 V, C
MIN.
TH
<45>
L
Hi-Z
Hi-Z
Hi-Z
Hi-Z
= 50 pF)
TH
1.5T + 31
<48>
<44>
MAX.
TI
<46>
Page 1428 of 1509
ns
ns
ns
ns
ns
ns
Unit