UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1095

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(13) UF0 INT status 2 register (UF0IS2)
Remark
UF0IS2
Bit position
This register indicates the interrupt source. If the contents of this register are changed, the EPCINT1B signal
becomes active.
This register is read-only, in 8-bit units.
If an interrupt request (INTUSBF0) is generated from USBF, the FW must read this register to identify the interrupt
source.
Each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bit of the UF0IC2 register.
The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 3, 7)
and the current setting of the interface.
7, 5
6, 4
0
BKI2IN
n = 1, 2
m = 1 and x = 7 where n = 1
m = 3 where n = 2
7
BKInIN
BKInDT
IT1DT
Bit name
BKI2DT
6
BKI1IN
These bits indicate that an IN token has been received in the UF0BIn register (Endpoint
m) and that NAK has been returned.
These bits indicate that the FIFO of the UF0BIn register (Endpoint m) has been toggled.
This means that data can be written to Endpoint m.
The data written to Endpoint m is transmitted in synchronization with the IN token next to
the one that set the BKInNK bit of the UF0EN register to 1. When the FIFO has been
toggled and then data can be written from the CPU, this bit is automatically set to 1 by
hardware. It is also set to 1 when the FIFO has been toggled, even if the data is a Null
packet. This bit is automatically cleared to 0 by hardware when the first write access is
made to the UF0BIn register.
These bits indicate that data has been correctly received from the UF0INT1 register
(Endpoint x).
Data is transmitted in synchronization with the IN token next to the one that set the ITnNK
bit of the UF0EN register to 1. This bit is automatically set to 1 by hardware when the
host has correctly received that data. It is automatically cleared to 0 by hardware when
the first write access is made to the UF0INT1 register. This bit is also set to 1 even when
the data is a Null packet.
5
1: IN token is received and NAK is transmitted (interrupt request is generated).
0: IN token is not received (default value).
1: FIFO has been toggled (interrupt request is generated).
0: FIFO has not been toggled (default value).
1: Transmission is completed (interrupt request is generated).
0: Transmission is not completed (default value).
BKI1DT
4
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
3
0
2
0
Function
1
0
IT1DT
0
00200024H
Address
Page 1095 of 1509
After reset
00H