UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 975

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(b) Write
Caution Do not set the TRQ bit and RDY bit to 1 at the same time. Be sure to set the RDY bit to 1
Cautions 1. Do not clear the RDY bit (0) during message transmission. Follow transmission abort
Caution Be sure to set the IE and RDY bits separately.
Caution Do not set the DN bit to 1 by software. Be sure to write 0 to bit 10.
Clear MOW
TRQ
RDY
Clear DN
0
1
0
1
Set IE
0
1
0
1
1
0
Other than above
before setting the TRQ bit to 1.
2. If the RDY bit is not cleared (0) even when the processing to clear it is executed, execute
3. Confirm, by reading the RDY bit again, that the RDY bit has been cleared (0) before writing
No message frame transmitting request that is pending or being transmitted is in the message buffer.
The message buffer is holding transmission of a message frame pending or is transmitting a message
frame.
The message buffer can be written by software. The CAN module cannot write to the message buffer.
Writing the message buffer by software is ignored (except a write access to the RDY, TRQ, DN, and MOW
bits). The CAN module can write to the message buffer.
procedures in order to clear the RDY bit for redefinition.
the clearing processing again.
data to the message buffer.
However, it is unnecessary to confirm that the TRQ or RDY bit has been set (1) or that the
DN or MOW bit has been cleared (0).
MOW bit is not changed.
MOW bit is cleared to 0.
DN bit is cleared to 0.
DN bit is not changed.
Clear IE
1
0
IE bit is cleared to 0.
IE bit is set to 1.
IE bit is not changed.
Message buffer transmission request bit
Message buffer ready bit
Setting of MOW bit
Setting of DN bit
Setting of IE bit
CHAPTER 20 CAN CONTROLLER
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