UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 728

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
17.4 Registers
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(1) UARTCn control register 0 (UCnCTL0)
The UCnCTL0 register is an 8-bit register that controls the UARTCn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 10H.
(n = 0 to 4)
UCnCTL0
After reset: 10H
UCnPWR
UCnPWR
UCnRXE
The UARTCn operation is controlled by the UCnPWR bit. The TXDCn pin output
is fixed to high level by clearing the UCnPWR bit to 0 (fixed to low level if
UCnOPT0.UCnTDL bit = 1).
UCnTXE
• To start transmission, set the UCnPWR bit to 1 and then set the UCnTXE bit to 1.
• To initialize the transmission unit, clear the UCnTXE bit to 0, wait for two cycles of
• To start reception, set the UCnPWR bit to 1 and then set the UCnRXE bit to 1.
• To initialize the reception unit, clear the UCnRXE bit to 0, wait for two periods of
To stop transmission, clear the UCnTXE bit to 0 and then UCnPWR bit to 0.
the base clock, and then set the UCnTXE bit to 1 again. Otherwise, initialization
may not be executed (for the base clock, see 17.7 (1) (a) Base clock).
To stop reception, clear the UCnRXE bit to 0 and then UCnPWR bit to 0.
the base clock, and then set the UCnRXE bit to 1 again. Otherwise, initialization
may not be executed (for the base clock, see 17.7 (1) (a) Base clock).
<7>
0
1
0
1
0
1
Disable UCRTCn operation (UCRTCn reset asynchronously)
Enable UCRTCn operation
Disable transmission operation
Enable transmission operation
Disable reception operation
Enable reception operation
R/W
UCnTXE UCnRXE UCnDIR UCnPS1 UCnPS0
<6>
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
Address: UC0CTL0 FFFFFA00H, UC1CTL0 FFFFFA10H,
<5>
UC2CTL0 FFFFFA20H, UC3CTL0 FFFFFA30H,
UC4CTL0 FFFFFA40H
Transmission operation enable
Reception operation enable
UCRTCn operation control
<4>
3
2
UCnCL
1
UCnSL
0
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