UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1134

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(5) UF0 bulk-out 1 register (UF0BO1)
UF0BO1
The UF0BO1 register is a 64-byte × 2 FIFO that stores data for Endpoint2. This register consists of two banks of
64-byte FIFOs each of which performs a toggle operation and repeatedly connects the buses on the SIE and CPU
sides. The toggle operation takes place when data is in the FIFO on the SIE side and when no data is in the FIFO
on the CPU side (counter value = 0).
This register is read-only, in 8-bit units. A write access to this register is ignored.
When the hardware receives data for Endpoint2 from the host, it automatically transfers the data to the UF0BO1
register. When the register correctly receives the data, a FIFO toggle operation occurs. As a result, the BKO1DT
bit of the UF0IS3 register is set to 1, the quantity of the received data is held by the UF0BO1L register, and an
interrupt request or DMA request is issued to the CPU. Whether the interrupt request or DMA request is issued can
be selected by using the DQBO1MS bit of the UF0IDR register.
Read the data held by the UF0BO1 register by FW, up to the value of the amount of data read by the UF0BO1L
register. When the correct received data is held by the FIFO connected to the SIE side and the value of the
UF0BO1L register reaches 0, the toggle operation of the FIFO occurs, and the BKO1NK bit of the UF0EN register
is automatically cleared to 0. If data greater than the value of the UF0BO1L register is read and if the FIFO toggle
condition is satisfied, the toggle operation of the FIFO occurs. As a result, the next packet may be read by mistake.
Note that, if the toggle condition is not satisfied, the first data is repeatedly read.
If overrun data is received while data is held by the FIFO connected to the CPU side, Endpoint2 stalls, and the
FIFO on the CPU side is cleared.
When the UF0BO1 register is read while no data is in it, an undefined value is read.
Caution Be sure to read all the data stored in this register.
The operation of the UF0BO1 register is illustrated below.
Bit position
7 to 0
BKO17
7
BKO17 to
BKO10
Bit name
BKO16
6
BKO15
These bits store data for Endpoint2.
5
BKO14
4
BKO13
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
3
BKO12
2
Function
BKO11
1
BKO10
0
00200108H
Address
Page 1134 of 1509
After reset
Undefined