MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1013

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC561MZP56

Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC561MZP56
Manufacturer:
FREESCALE
Quantity:
852
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC561MZP56
Manufacturer:
FREESCALE
Quantity:
852
Company:
Part Number:
MPC561MZP56
Quantity:
13
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
24.8.2.4.4
For compressed code support, six additional bits indicate the starting bit address within the word of the
compressed instruction. The program trace indirect branch synchronization with compressed code
message has the following formats depending on the setting of MC[PTSM]:
Bit pointer format is shown in
24.8.2.4.5
When more than 256 instructions have run without a branch being taken a program trace resource full
message will be generated that indicates the maximum I-CNT value has been reached. The I-CNT field
has a maximum width of 8 bits.
Freescale Semiconductor
:
:
[6 bits]
Figure 24-30. Indirect Branch Synchronization Message Format with Compressed
Figure 24-31. Indirect Branch Synchronization Message Format with Compressed
Figure 24-28. Direct Branch Synchronization Message Format with Compressed
Figure 24-29. Direct Branch Synchronization Message Format with Compressed
TCODE (61)
Indirect Branch Synchronization Message with Compressed Code
Resource Full Message
[6 bits]
[6 bits]
TCODE (60)
TCODE (60)
[6 bits]
TCODE (60)
Figure 24-22
MPC561/MPC563 Reference Manual, Rev. 1.2
Max Length = 35 bits
Min Length = 13 bits
Max Length = 43 bits
Min Length = 14 bits
Max Length = 43 bits
Min Length = 14 bits
[6 bits]
Sequence Count
Sequence Count
Bit Pointer
Max Length = 35 bits
Min Length = 13 bits
Bit address
[1-8 bits]
[1-8 bits]
Code (PTSM = 0)
Code (PTSM = 1)
Code (PTSM = 1)
and bit address format is described in
Code (PTSM - 0)
[6 bits]
Full target address
[1 – 23 bits]
Bit address
Bit Pointer
[6 bits]
Full target address
[6 bits]
[1 – 23 bits]
Full target address
Full target address
[1 – 23 bits]
[1 – 23 bits]
Table
24-26.
READI Module
24-45

Related parts for MPC561MZP56