MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 289

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Chapter 7
Reset
This section describes the MPC561/MPC563 reset sources, operation, control, and status.
7.1
The MPC561/MPC563 has several inputs to the reset logic which include the following:
All of these reset sources are fed into the reset controller. The control logic determines the cause of the
reset, synchronizes it, and resets the appropriate logic modules, depending on the source of the reset. The
memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized only
on hard reset. External soft reset initializes internal logic while maintaining system configuration.
The reset status register (RSR) reflects the most recent source to cause a reset.
7.1.1
The power-on reset pin, PORESET, is an active low input. In a system with power-down low-power mode,
this pin should be activated only as a result of a voltage failure on the KAPWR pin. After detecting the
assertion of PORESET, the MPC561/MPC563 enters the power-on reset state. During this state the
MODCK[1:3] signals determine the oscillator frequency, PLL multiplication factor, and the PITRTCLK
and TMBCLK clock sources. In addition, the MPC561/MPC563 asserts the SRESET and HRESET pins
at the rising edge of PORESET.
The PORESET pin should be asserted for a minimum time of 100,000 of clock oscillator cycles after a
valid level has been reached on the KAPWR supply. After detecting the assertion of PORESET, the
MPC561/MPC563 remains in the power-on reset state until the last of the following two events occurs:
Freescale Semiconductor
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Power-on reset
External hard reset pin (HRESET)
External soft reset pin (SRESET)
Loss of PLL lock
On-chip clock switch
Software watchdog reset
Checkstop reset
Debug port hard reset
Debug port soft reset
JTAG reset
Illegal bit change (ILBC)
Reset Operation
Power-On Reset
MPC561/MPC563 Reference Manual, Rev. 1.2
7-1