MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 950

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Development Support
Data values in the last two functions other than those specified are reserved.
All transmissions from the debug port on DSDO begin with a “0” or “ready” bit. This indicates that the
CPU is trying to read an instruction or data from the port. The external development tool must wait until
it sees DSDO go low to begin sending the next transmission.
The control bit differentiates between instructions and data and allows the development port to detect that
an instruction was entered when the CPU was expecting data and vice versa. If this occurs a sequence error
indication is shifted out in the next serial transmission.
The trap enable function allows the development tool to transfer data to the trap enable control register.
The debug port command function allows the development tool to either negate breakpoint requests, reset
the processor, activate or deactivate the fast down load procedure.
The NOP function provides a null operation for use when there is data or a response to be shifted out of
the data register and the appropriate next instruction or command will be determined by the value of the
response or data shifted out.
23.4.6.10 Serial Data Out of Development Port
The encoding of data shifted out of the development port shift register in debug mode (through the DSDO
pin) is the same as for trap enable mode and is shown in
Valid data encoding is used when data has been transferred from the CPU to the development port shift
register. This is the result of an instruction to move the contents of a general purpose register to the debug
port data register (DPDR). The valid data encoding has the highest priority of all status outputs and will
be reported even if an interrupt occurs at the same time. Since it is not possible for a sequencing error to
occur and also have valid data there is no priority conflict with the sequencing error status. Also, any
interrupt that is recognized at the same time that there is valid data is not related to the execution of an
23-36
1
Start
Refer to
1
1
1
1
1
Table 23-13. Debug Instructions / Data Shifted into Development Port Shift Register
Table 23-10
Mode
0
0
1
1
1
Control
0
1
0
1
1
Trap enable
0011111
Bits 0:6
MPC561/MPC563 Reference Manual, Rev. 1.2
0
1
Instruction / Data (32 Bits)
CPU Instruction
CPU Data
Does not exist
Does not exist
Does not exist
Bits 7:31
Table
23-12.
Negate breakpoint requests
Transfer Instruction
Control Register
Transfer data to
Transfer Data
Trap Enable
to the CPU.
Freescale Semiconductor
Function
to CPU
to CPU
NOP