MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1161

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
0
ADDRESS OFFSETS
0x30XX(W+1)C
0x30XX(W+3)A
0x30XX(W+1)A
0x30XX(W+1)0
0x30XX(W+1)2
0x30XX(W+1)4
0x30XX(W+1)6
0x30XX(W+1)8
1
2
0
0
0
:
3
1
1
1
0
0
= Written By RCPU
= Written By TPU
Channel Function Select
Host Sequence
Host Service Request
Channel Priority
Channel Interrupt Enable 0 – Channel Interrupt Disabled
Channel Interrupt Status
1
1
1.
NAME
0
Optional additional parameters not available in all cases. Refer to Freescale Programming
Note TPUPN04/D for details.
Figure D-5. TSM Parameters — Slave Mode
1
MPC561/MPC563 Reference Manual, Rev. 1.2
ACCEL_RATIO_14
ACCEL_RATIO_36
ACCEL_RATIO_10
ACCEL_RATIO_12
ACCEL_RATIO_2
ACCEL_RATIO_4
ACCEL_RATIO_6
ACCEL_RATIO_8
2
3
:
xxxx – TSM Function Number. Assigned
during microcode assembly. See
x0 – Rotate Pin_Sequence Once
x1 – Split Mode Acceleration Table
1x – Rotate Pin_Sequence Once Between Steps
1x – Rotate Pin_Sequence Twice Between Steps
00 – No Host Service (Reset Condition)
01 – Initialize, Pin Low
10 – Initialize, Pin High
11 – Move Request (Master Only)
00 – Disabled
01 – Low Priority
10 – Medium Priority
11 – High Priority
1 – Channel Interrupt Enabled
0 – Channel Interrupt Not Asserted
1 – Channel Interrupt Asserted
4
PARAMETER RAM
CONTROL BITS
Between Steps
= Written by RCPU and TPU
= Unused Parameters
5
1
1
6
7
OPTIONS
BITS
8
9
ACCEL_RATIO_13
ACCEL_RATIO_35
ACCEL_RATIO_11
ACCEL_RATIO_1
ACCEL_RATIO_3
ACCEL_RATIO_5
ACCEL_RATIO_7
ACCEL_RATIO_9
10 11 12 13 14 15
Table D-1
:
W = Channel Number
For address offsets: XX=41 for
TPU_A, 45 for TPU_B
YY=40 for TPU_A, 44
for TPU_B
See
PRAM Address Offset Map.
Table 19-24
0x30YY1C – 0x30YY1E
0x30YY0C – 0x30YY12
0x30YY18 – 0x30YY1A
0x30YY14 – 0x30YY16
1
1
ADDRESSES
0x30YY0A
0x30YY20
TPU3 ROM Functions
for the
Param 0
Param 1
Param 2
Param 3
Param 4
Param 5
Param 6
Param 29
:
D-9