MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 665
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MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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15.7.3
SCCxR1 contains SCIx configuration parameters, including transmitter and receiver enable bits, interrupt
enable bits, and operating mode enable bits. The CPU can read or write this register at any time. The SCI
can modify the RWU bit under certain circumstances.
Changing the value of SCCxR1 bits during a transfer operation can disrupt the transfer. Before changing
register values, allow the SCI to complete the current transfer, then disable the receiver and transmitter.
Freescale Semiconductor
SRESET
Bits
Field
0
1
2
3
4
5
6
7
8
9
Addr
SCI Control Register 1 (SCCxR1)
MSB
LOOPS
—
WOMS
WAKE
0
Name
TCIE
TIE
ILT
PE
PT
—
M
LOOPS WOMS ILT
1
Reserved
Loop mode
0 Normal SCI operation, no looping, feedback path disabled.
1 SCI test operation, looping, feedback path enabled.
Wired-OR mode for SCI Pins
0 If configured as an output, TXD is a normal CMOS output.
1 If configured as an output, TXD is an open drain output.
Idle-line detect type. Refer to
0 Short idle-line detect (start count on first one).
1 Long idle-line detect (start count on first one after stop bit(s)).
Parity type. Refer to
0 Even parity.
1 Odd parity.
Parity enable. Refer to
0 SCI parity disabled.
1 SCI parity enabled.
Mode select. Refer to
0 10-bit SCI frame.
1 11-bit SCI frame.
Wakeup by address mark. Refer to
0 SCI receiver awakened by idle-line detection.
1 SCI receiver awakened by address mark (last bit set).
Transmit interrupt enable
0 SCI TDRE interrupts disabled.
1 SCI TDRE interrupts enabled.
Transmit complete interrupt enable
0 SCI TC interrupts disabled.
1 SCI TC interrupts enabled.
2
Figure 15-27. SCI Control Register 1 (SCCxR1)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 15-25. SCCxR1 Bit Descriptions
3
PT
Section 15.7.7.4, “Parity
4
Section 15.7.7.2, “Serial
Section 15.7.7.4, “Parity
PE
5
0000_0000_0000_0000
Section 15.7.7.9, “Idle-Line
0x30 500A; 0x30 5022
M
6
Section 15.7.7.10, “Receiver
WAKE TIE TCIE RIE
7
Description
Checking.”
Formats.”
Checking.
8
9
Detection.”
10
Wake-Up.”
Queued Serial Multi-Channel Module
ILIE
11
TE
12
RE RWU SBK
13
14
LSB
15
15-47
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