MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 926
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MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Development Support
comparator when working in half-word mode and to the correct bytes of the data comparator when
working in byte mode.
Since bytes and half-words can be accessed using a larger data width instruction, it is impossible to predict
the exact value of the L-address lines when the requested byte/half-word is accessed, (e.g., if the matched
byte is byte two of the word and it is accessed using a load word instruction), the L-address value will be
of the word (byte zero). Therefore, the CPU masks the two least-significant bits of the L-address
comparators whenever a word access is performed and the least-significant bit whenever a half-word
access is performed.
Address range is supported only when aligned according to the access size. (See
“Examples”).
23.2.1.3
23-12
•
•
A fully supported scenario:
— Looking for:
— Programming options:
— Result:
A fully supported scenario:
— Looking for:
— Programming option:
— Result:
Data size: Byte
Address: 0x00000003
Data value: greater than 0x07 and less than 0x0c
One L-address comparator = 0x00000003 and program for equal
One L-data comparator = 0x00000007 and program for greater than
One L-data comparator = 0x0000000c and program for less than
Both byte masks = 0xe
Both L-data comparators program to byte mode
The event will be correctly detected regardless of the load/store instruction the compiler
chooses for this access
Data size: half-word
Address: greater than 0x00000000 and less than 0x0000000c
Data value: greater than 0x4e204e20 and less than 0x9c409c40
One L-address comparator = 0x00000000 and program for greater than
One L-address comparator = 0x0000000c and program for less than
One L-data comparator = 0x4e204e20 and program for greater than
One L-data comparator = 0x9c409c40 and program for less than
Both byte masks = 0x0
Both L-data comparators program to half-word mode
The event will be correctly detected as long as the compiler does not use a load/store instruction
with data size of byte.
Examples
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 23.2.1.3,
Freescale Semiconductor
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