MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 579

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Therefore, conversion time requires a minimum of 14 QCLK clocks (seven µs with a 2.0-MHz QCLK). If
the maximum final sample time period of 8 QCLKs is selected, the total conversion time is 20 QCLKs (10
µs with a 2.0-MHz QCLK)
Figure 14-21
14.3.12 Channel Decode and Multiplexer
The internal multiplexer selects one of the 16 analog input signals for conversion. The selected input is
connected to the sample buffer amplifier. The multiplexer also includes positive and negative stress
protection circuitry, which prevents deselected channels from affecting the selected channel when current
is injected into the deselected channels. Refer to
current levels.
14.3.13 Sample Buffer Amplifier
The sample buffer is used to raise the effective input impedance of the A/D converter, so that external
components (higher bandwidth or higher impedance) are less critical to accuracy. The input voltage is
buffered onto the sample capacitor to reduce crosstalk between channels.
14.3.14 Digital to Analog Converter (DAC) Array
The digital to analog converter (DAC) array consists of binary-weighted capacitors and a resistor-divider
chain. The reference voltages, V
DAC also converts the following three internal channels:
The DAC array serves to provide a mechanism for the successive approximation A/D conversion.
Freescale Semiconductor
•
•
•
QCLK
V
V
(V
RH
RL
RH
— Reference voltage low
— Reference voltage high
– V
illustrates the timing for conversions.
RL
)/2 — Reference voltage
RH
“Buffer”
2 cycles
Sample
MPC561/MPC563 Reference Manual, Rev. 1.2
Time
Sample Time
and V
Figure 14-21. Conversion Timing
RL
“Final” Sample
N cycles:
(2 or 8)
, are used by the DAC to perform ratiometric conversions. The
Time
Appendix F, “Electrical
Successive Approximation Resolution
Sequence
Resolution (“Conv”)
10 cycles
Time
Characteristics,” for specific
QADC64E Enhanced Mode Operation
14-37