MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 500

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

QADC64E Legacy Mode Operation
13.4.2
The internal multiplexer selects one of the 16 analog input signals for conversion. The selected input is
connected to the sample buffer amplifier. The multiplexer also includes positive and negative stress
protection circuitry, which prevents deselected channels from affecting the selected channel when current
is injected into the deselected channels. Refer to
current levels.
13.4.3
The sample buffer is used to raise the effective input impedance of the A/D converter, so that external
components (higher bandwidth or higher impedance) are less critical to accuracy. The input voltage is
buffered onto the sample capacitor to reduce crosstalk between channels.
13.4.4
The digital to analog converter (DAC) array consists of binary-weighted capacitors and a resistor-divider
chain. The reference voltages, V
DAC also converts the following three internal channels:
The DAC array serves to provide a mechanism for the successive approximation A/D conversion.
Resolution begins with the most significant bit (MSB) and works down to the least significant bit (LSB).
The switching sequence is controlled by the comparator and successive-approximation register (SAR)
logic.
13-36
•
•
•
•
V
V
(V
Sample capacitor — The sample capacitor is employed to sample and hold the voltage to be
converted.
RH
RL
RH
— Reference voltage low
Channel Decode and Multiplexer
Sample Buffer Amplifier
Digital-to-Analog Converter (DAC) Array
— Reference voltage high
– V
RL
QCLK
)/2 — Reference voltage
(2, 4, 8, 16)
N cycles:
Sample
Sample
Time
Time
Figure 13-22. Bypass Mode Conversion Timing
RH
MPC561/MPC563 Reference Manual, Rev. 1.2
and V
RL
Successive Approximation Resolution
, are used by the DAC to perform ratiometric conversions. The
Appendix F, “Electrical
Resolution
Sequence
10 cycles
Time
Characteristics,” for specific
Freescale Semiconductor