MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 469

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

enhanced mode. This will be described in
Modes of
13.2.4
The heart of the QADC is its conversion command word (CCW) queues. This is where the module is
programmed to convert a particular channel according to a particular requirement. The queues are created
by writing CCWs into the CCW table in the register memory. The queues are controlled by the three
control registers, and their status can be read from the two status registers. As conversions are completed
the digital value is written into the result word table.
word table.
13.2.5
The QADC can use from one to four 8-input external multiplexer chips to expand the number of analog
signals that may be converted. The externally multiplexed channels are automatically selected from the
Freescale Semiconductor
Operation.”
P = Pause Until Next Trigger
BYP = Bypass Buffer Amplifier
IST = Input Sample Time
CHAN = Channel Number and End_of_Queue Code
Using the Queue and Result Word Table
External Multiplexing
BQ2
MSB
00
6
P BYP IST
10-bit Conversion
Conversion Command
Command Word
Word (CCW) Table
(CCW) Format
Begin Queue 1
End of Queue 1
Begin Queue 2
7
End of Queue 2
Figure 13-2. QADC64E Conversion Queue Operation
8
9 10
MPC561/MPC563 Reference Manual, Rev. 1.2
CHAN
Section 13.3.1.3, “Switching Between Legacy and Enhanced
15
LSB
Analog to Digital
Channel Select,
Sample, Hold,
Conversion
A/D Converter
and
Figure 13-2
Right Justified, Unsigned Result Format
MSB
0 0
S
Left Justified, Unsigned Result Format
0
0
0
Left Justified, Signed Result Format
1
0 0 0
in Three Different 16-bit Formats
Result
Result
shows the CCW queue and the result
0
5 6
Software Readable
10-bit Result is
Result Word Table
Result
9 10
9 10
0 0
0 0
QADC64E Legacy Mode Operation
0 0 0
0
0 0
LSB
15
15
15
0
0
00
13-5