MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 395
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Note: the delay for the internal to external cycle may be one clock or greater.
9.5.14
Show cycles are representations of RCPU accesses to internal devices of the MPC561/MPC563. These
accesses are driven externally for emulation, visibility, and debugging purposes. A show cycle can have
one address phase and one data phase, or just an address phase in the case of instruction show cycles. The
cycle can be a write or a read access. The data for both the read and write accesses should be driven by the
bus master. (This is different from normal bus read and write accesses.) The address and data of the show
cycle must each be valid on the bus for one clock. The data phase must not require a transfer acknowledge
to terminate the bus show cycle.
Freescale Semiconductor
CLKOUT
BR
BG (output)
BB
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
RETRY (output)
Show Cycle Transactions
Figure 9-40. Retry of External Master Access (Internal Arbiter)
ADDR (external)
MPC561/MPC563 Reference Manual, Rev. 1.2
O
Allow Internal
Access to Gain the
Bus
ADDR (internal)
External Bus Interface
9-55
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