MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 421

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Note: Timing in this table refers to the typical timing only. Consult the electrical characteristics for exact worst-case timing values.
Additional timing rules not covered in
Freescale Semiconductor
•
•
•
•
•
•
TRLX
1/4 clock actually means 0 to 1/4 clock, 1/2 clock means 1/4 to 1/2 clock.
0
1
1
1
1
1
1
1
1
1
If SETA = 1, an external TA signal is required to terminate the cycle.
If TRLX = 1 and SETA = 1, the minimum cycle length = 3 clock cycles (even if SCY = 0000)
If TRLX = 1, the number of wait states = 2 ∗ SCY & 2 ∗ BSCY
ACS = 01 is not defined (reserved).
If EHTR = 1, an extra (idle) clock cycle is inserted between a read cycle and a following read cycle
to another region, or between a read cycle and a following write cycle to any region.
If LBDIP = 1 (late BDIP assertion), the BDIP signal is asserted only after the number of wait states
for the first beat in a burst have elapsed. See
as well as
Access
Type
write
write
write
write
write
write
write
read
read
read
The LBDIP/TBDIP function can operate only when the cycle termination is
internal, using the number of wait states programmed in one of the ORx
registers. The LBDIP/TBDIP function cannot be activated at the same
time—results are unknown.
Section 9.5.5, “Burst
ACS
11
00
10
11
00
10
11
00
10
11
Table 10-3. Programming Rules for Timing Strobes (continued)
CSNT
X
X
X
1
0
0
0
1
1
1
MPC561/MPC563 Reference Manual, Rev. 1.2
1/2 * clock
(1 + 1/4) *
(1 + 1/2) *
(1 + 1/4) *
(1 + 1/2) *
(1 + 1/4) *
(1 + 1/2) *
Asserted
Address
to CS
clock
clock
clock
clock
clock
clock
0
0
0
Table 10-3
Mechanism.”
Negated to
1/2 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
Add/Data
(1 + 1/2) *
(1 + 1/2) *
Invalid
clock
clock
CS
NOTE
include the following:
Figure 9-13
Address to
WE/BE or
3/4 * clock
(1 + 3/4) *
(1 + 3/4) *
(1 + 3/4) *
Asserted
3/4 clock
3/4 clock
3/4 clock
(1 + 3/4)
(1 + 3/4)
(1 + 3/4)
clock
clock
clock
clock
clock
clock
OE
in
Chapter 9, “External Bus
Negated to
1/2 * clock
1/4 * clock
1/4 * clock
1/4 * clock
Add/Data
(1 + 1/2) *
(1 + 1/2) *
(1 + 1/2) *
WE/BE
Invalid
clock
clock
clock
X
X
X
Negated to
1/4 * clock
1/4 * clock
1/4 * clock
Add/Data
Invalid
OE
X
X
X
X
X
X
X
Memory Controller
Number of
2 + SCY
2 * SCY
2 * SCY
2 * SCY
2 * SCY
2 * SCY
2 * SCY
2 * SCY
2 * SCY
2 * SCY
Cycles
Interface,”
Total
2 +
3 +
3 +
2 +
3 +
3 +
3 +
4 +
4 +
10-23