MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 399
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 10
Memory Controller
The memory controller generates interface signals to support a glueless interface to external memory and
peripheral devices. It supports four regions, each with its own programmed attributes. The four regions are
controlled by four chip-select signals. Read and write strobes are also provided.
The memory controller operates in parallel with the external bus interface to support external cycles. When
an access to one of the memory regions is initiated, the memory controller takes ownership of the external
signals and controls the access until its termination. Refer to
10.1
The memory controller provides a glueless interface to external EPROM, static RAM (SRAM), Flash
(EEPROM), and other peripherals. The general-purpose chip-selects are available on lines CS0 through
CS3. CS0 also functions as the global (boot) chip-select for accessing the boot Flash EEPROM. The chip
select allows zero to 30 wait states.
Figure 10-2
Freescale Semiconductor
Internal Bus
Overview
is a block diagram of the MPC561/MPC563 memory controller.
Interface
U-bus
Figure 10-1. Memory Controller Function within the USIU
MPC561/MPC563 Reference Manual, Rev. 1.2
Memory Controller
EBI Bus
Bus
External Bus
Controller
Figure
Memory
Interface
10-1.
ADDR[0:31]
DATA[0:31]
Control Bus
WE[0:3]/BE[0:3]
OE
CS[0:3]
10-1
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