MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 669

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

15.7.6
The RXD1 and RXD2 pins are the receive data pins for the SCI1 and SCI2, respectively. TXD1 and TXD2
are the transmit data pins for the two SCI modules. The pins and their functions are listed in
15.7.7
The SCI can operate in polled or interrupt-driven mode. Status flags in SCxSR reflect SCI conditions
regardless of the operating mode chosen. The TIE, TCIE, RIE, and ILIE bits in SCCxR1 enable interrupts
for the conditions indicated by the TDRE, TC, RDRF, and IDLE bits in SCxSR, respectively.
15.7.7.1
Bit-time
Start bit
Stop bit
Freescale Semiconductor
SRESET
Bits
7:15
0:6
Field
Addr
Transmit Data
Receive Data
SCI Pins
SCI Operation
Pin Names
Definition of Terms
R[8:0]/
Name
T[8:0]
MSB
0
—
1
Reserved
R[7:0]/T[7:0] contain either the eight data bits received when SCxDR is read, or the eight data
bits to be transmitted when SCxDR is written. R8/T8 are used when the SCI is configured for
nine-bit operation (M = 1). When the SCI is configured for 8-bit operation, R8/T8 have no
meaning or effect.
Accesses to the lower byte of SCxDR triggers the mechanism for clearing the status bits or for
initiating transmissions whether byte, half-word, or word accesses are used.
The time required to transmit or receive one bit of data, which is equal to one cycle
of the baud frequency.
One bit-time of logic zero that indicates the beginning of a data frame. A start bit
must begin with a one-to-zero transition and be preceded by at least three receive
time samples of logic one.
One bit-time of logic one that indicates the end of a data frame.
2
0000_000
—
3
RXD1, RXD2
TXD1, TXD2
Figure 15-29. SCI Data Register (SCxDR)
MPC561/MPC563 Reference Manual, Rev. 1.2
Mnemonic
Table 15-27. SCxDR Bit Descriptions
4
Table 15-28. SCI Pin Functions
5
6
R8/T8 R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0
Receiver disabled
Receiver enabled
Transmitter disabled
Transmitter enabled
7
0x30 500E
Mode
8
Description
9
10
General purpose input
Serial data input to SCI
General purpose output
Serial data output from SCI
Undefined
11
Queued Serial Multi-Channel Module
Function
12
13
14
Table
LSB
15
15-28.
15-51