MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 412

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Memory Controller
The CSx timing is defined by the setup time required between the address lines and the CE line. The
memory controller allows specification of the CS timing to meet the setup time required by the peripheral
device. This is accomplished through the ACS field in the base register. In
set to 0b11, so CSx is asserted half a clock cycle after the address lines are valid.
10.3.3
The TRLX field is provided for memory systems that need a more relaxed timing between signals. When
TRLX is set and ACS = 0b00, the memory controller inserts an additional cycle between address and
strobes (CS line and WE/OE).
When TRLX and CSNT are both set in a write to memory, the strobe lines (WE/BE[0:3] and CS, if ACS
= 0b00) are negated one clock earlier than in the regular case.
Figure 10-11
10-14
•
•
Strobes (OE and CS) assertion time is delayed one clock relative to address (TRLX bit set effect).
Strobe (CS) is further delayed (half-clock) relative to address due to ACS field being set to 11.
Relaxed Timing Examples
Address
shows a read access with relaxed timing. Note the following:
CLOCK
RD/WR
In the case of a bank selected to work with external transfer acknowledge
(SETA = 1) and TRLX = 1, the memory controller does not support external
devices that provide TA to complete the transfer with zero wait states. The
minimum access duration in this case equals three clock cycles.
Data
CS
TS
TA
Figure 10-10. Peripheral Devices Basic Timing (ACS = 11, TRLX = 0)
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
ACS = 11
Figure
10-10, the ACS bits are
CSNT = 1
Freescale Semiconductor