MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 153

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Table 3-2
Configuration and
Buffer Controller 2
Freescale Semiconductor
lists the MPC561/MPC563 supervisor-level registers; refer also to
Protection,”
Module,” for more information.
SPR Number
(Decimal)
272
273
274
275
284
285
18
19
22
26
27
80
81
82
Chapter 11, “L-Bus to U-Bus Interface
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 3-2. Supervisor-Level SPRs
DAE/Source Instruction Service Register (DSISR)
See
Register
Data Address Register (DAR)
See
descriptions.
Decrementer Register (DEC)
See
descriptions.
Save and Restore Register 0 (SRR0)
See
Register 0
Save and Restore Register 1 (SRR1)
See
Register 1
External Interrupt Enable (EIE)
See
Special-Purpose
External Interrupt Disable (EID)
See
Special-Purpose
Non-Recoverable Interrupt (NRI)
See
Special-Purpose
SPR General 0 (SPRG0)
See
for bit descriptions.
SPR General 1 (SPRG1)
See
for bit descriptions.
SPR General 2 (SPRG2)
See
for bit descriptions.
SPR General 3 (SPRG3)
See
for bit descriptions.
Time Base Lower – Write (TBL)
See
Time Base Upper – Write (TBU)
See
Section 3.9.2, “DAE/Source Instruction Service
Section 3.9.3, “Data Address Register
Section 6.1.6, “Decrementer
Section 3.9.6, “Machine Status Save/Restore
Section 3.9.7, “Machine Status Save/Restore
Section 3.9.10.1, “EIE, EID, and NRI
Section 3.9.10.1, “EIE, EID, and NRI
Section 3.9.10.1, “EIE, EID, and NRI
Section 3.9.8, “General SPRs
Section 3.9.8, “General SPRs
Section 3.9.8, “General SPRs
Section 3.9.8, “General SPRs
Section 6.1.7, “Time Base
Section 6.1.7, “Time Base
(DSISR),” for bit descriptions.
(SRR0),” for bit descriptions.
(SRR1),” for bit descriptions.
Special-Purpose Register
Registers.”
Registers.”
Registers.”
1
1
1
(TB).”
(TB).”
1
1
(DEC).” for bit
(SPRG0–SPRG3),”
(SPRG0–SPRG3),”
(SPRG0–SPRG3),”
(SPRG0–SPRG3),”
(L2U),” and
(DAR),” for bit
Chapter 6, “System
Chapter 4, “Burst
Central Processing Unit
3-9