MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 794
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MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Modular Input/Output Subsystem (MIOS14)
17.11.4 Modular I/O Bus (MIOB) Interface
17.11.5 Effect of RESET on MPIOSM
When the RESET signal is asserted, all the DDR bits are cleared. The data bits are undefined after reset.
17.11.6 MPIOSM Testing
No special test logic has been implemented in this submodule. To be flexible while selecting the number
of implemented signals, the test patterns are implemented in a bit per bit modular fashion.
17.11.7 MPIOSM Registers
The privilege level to access to the MPIOSM registers depends on the MIOS14MCR[SUPV]. The
privilege level is unrestricted after reset and can be change to supervisor by software.
17.11.8 MPIOSM Register Organization
17.11.8.1 MPIOSM Data Register (MPIOSMDR)
17-62
•
•
•
0x30 6100
0x30 6102
0x30 6104
0x30 6106
SRESET
The MPIOSM is connected to all the signals in the read/write and control bus, to allow data transfer
from and to the MPIOSM registers, and to control the MPIOSM in the different possible situations.
The MPIOSM does not use the counter bus set and is therefore not connected to it.
The MPIOSM does not generate any interrupts and is therefore not connected to this bus.
Field Data
Addr
MSB
15
MSB
0
0
Data
14
1
1
Data
13
2
2
Figure 17-32. MPIOSM Data Register (MPIOSMDR)
Figure 17-31. MPIOSM — Register Organization
Data
12
3
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Data
11
4
MPIOSM Data Direction Register (MPIOSMDDR)
4
Data
MPIOSM Data Register (MPIOSMDR)
10
5
5
Data
9
6
6
Data
0x30 6100
Undefined
Reserved
Reserved
8
7
7
Data
7
8
8
Data
6
9
9
Data
10
10
5
Data
11
11
4
Data
12
12
3
Freescale Semiconductor
Data
13
13
2
Data
14
14
1
Data
LSB
15
15
0
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