MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 475

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

access mode. Assignable data space can be either restricted to supervisor-only access or unrestricted to
both supervisor and user data space accesses. The SUPV bit in the QADCMCR designates the assignable
space as supervisor or unrestricted.
The following information applies to accesses to address space located within the module’s 16-bit
boundaries and where the response is a bus error. See
The bus master indicates the supervisor and user space access with the function code bits (FC[2:0]) on the
IMB3. For privilege violations, refer to the
consequence of a bus error cycle termination.
Freescale Semiconductor
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Attempts to read a supervisor-only data space when not in the supervisor access mode and
SUPV = 1, causes the bus master to assert a bus error condition. No data is returned. If SUPV = 0,
the QADC64E asserts a bus error condition and no data is returned.
Attempts to write to supervisor-only data space when not in the supervisor access mode and
SUPV = 1, causes the bus master to assert a bus error condition. No data is written. If SUPV = 0,
the QADC64E asserts a bus error condition and the register is not written.
Attempts to read unimplemented data space in the unrestricted access mode and SUPV = 1, causes
the bus master to assert a bus error condition and no data is returned. In all other attempts to read
unimplemented data space, the QADC64E causes a bus error condition and no data is returned.
Attempts to write unimplemented data space in the unrestricted access mode and SUPV = 1, causes
the bus master to assert a bus error condition and no data is written. In all other attempts to write
unimplemented data space, the QADC64E causes a bus error condition and no data is written.
Attempts to read assignable data space in the unrestricted access mode when the space is
programmed as supervisor space causes the bus master to assert a bus error condition and no data
is returned.
Attempts to write assignable data space in the unrestricted access mode when the space is
programmed as supervisor space causes the bus master to assert a bus error condition and the
register is not written.
1
2
3
4 Access to QADCTEST register will act as a reserved/unimplemented register unless in factory
Mode
S/U = Supervisor/Unrestricted
QADC64E bus error = Caused by QADC64E
Master bus error = Caused by bus master
test mode
S/U
U
U
S
S
1
SUPV Bit
0
1
0
1
Table 13-6. QADC64E Bus Error Response
MPC561/MPC563 Reference Manual, Rev. 1.2
QADC64E bus error
Supervisor-Only
Master bus error
Valid access
Valid access
Register
Chapter 9, “External Bus
3
2
Unrestricted Register
Table 13-6
Master bus error
Valid access
Valid access
Valid access
Supervisor/
for more information.
4
3
Interface” to determine the
QADC64E bus error
QADC64E bus error
QADC64E bus error
Master bus error
Unimplemented
QADC64E Legacy Mode Operation
Reserved/
Register
3
2
2
2
13-11