MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 396
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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External Bus Interface
Show cycles are activated by properly setting the SIUMCR register bits. Refer to
Module Configuration Register
in the ICTRL register. Refer to
L2U_MCR register. Refer to
In a burst show cycle only the first data beat is shown externally. Refer to
transaction encodings.
Instruction show cycle bus transactions have the following characteristics (see
The compressed address is driven on the external bus in the following manner:
See
Features” for more details about decompression mode.
9-56
•
•
•
•
•
•
Chapter 4, “Burst Buffer Controller 2
One clock cycle
Address phase only; in decompression on mode part of the compressed address is driven on data
lines together with address lines. The external bus interface adds one clock delay between a read
cycle and such show cycle.
STS assertion only (no TA assertion)
ADDR[0:29] = the word base address;
DATA[0] = operating mode:
— 0 = decompression off mode;
— 1 = decompression on mode;
DATA[1:4] = bit pointer
Table
Table
(SIUMCR).” Construction visibility is controlled by the ISCT_SER bits
MPC561/MPC563 Reference Manual, Rev. 1.2
11-7.
23-26. Data visibility is controlled by the LSHOW bits of the
Module” and
Appendix A, “MPC562/MPC564 Compression
Table 9-8
Figure
Section 6.2.2.1.1, “SIU
Freescale Semiconductor
for show cycle
9-41):
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