MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1418

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

TouCAN
TPU
Index-18
address
bit timing configuration 16-8
external pins 16-2
initialization sequence 16-12
interrupts 16-20
message buffer address map 16-24
operation 16-3
receive process 16-14
registers
special operating modes 16-17
transmit process 16-13
features 16-1
address map 19-8
components 19-2
FREEZE flag (TPUF) 19-14
function library 19-4
host interface 19-2
interrupts 19-5
microengine 19-2
operation 19-3
parameter RAM 19-2
map 16-21
control register 0 (CANCTRL0) 16-27
control register 1 (CTRL1) 16-8
control register 1(CANCTRL1) 16-28
control register 2 (CANCTRL2) 16-30
control register 2 (CTRL2) 16-8
error and status register (ESTAT) 16-33
free running timer register (TIMER) 16-31
interrupt
module configuration register (TCNMCR) 16-25
receive
RX/TX error counter registers
test configuration register (CANTCR) 16-27
auto power save mode 16-19
debug mode 16-17
low-power stop mode 16-18
coherency 19-4
emulation support 19-4
event timing 19-3
interchannel communication 19-4
programmable channel service priority 19-4
address map 19-23
configuration register (CANICR) 16-27
flag register (IFLAG) 16-36
mask register (IMASK) 16-35
buffer 14 mask registers (RX14MSKHI/LO) 16-32
buffer 15 mask registers (RX15MSKHI/LO) 16-33
global mask registers (RXGMSKLO/HI 16-31
(RXECTR/TXECTR) 16-36
,
19-23
,
16-10
MPC561/MPC563 Reference Manual, Rev. 1.2
TPU Reference Manual 19-3
TPU2
TPU3 Emulation Mode Operation 20-7
TPUF 19-14
TPUMCR 19-11
TPUMCR2 19-19
TR 23-42
trace indicators 23-4
trace interrupt, 3-54
transaction (bus), 9-8
Transfer
transfer acknowledge (TA), 9-40
transfer code 24-4
transfer error acknowledge (TEA), 9-40
transfer size (TSIZ), 9-38
transfer start (TS) 9-37
transfers
Transmission
Transmit
registers
scheduler 19-2
time
timer channels 19-2
module configuration register 2 (TPUMCR2) 19-19
length options 15-37
time 13-35
alignment and packaging 9-29
burst-inhibited 9-18
termination signals 9-40
complete
/receive status (TX/RX) 16-34
bit error (BITERR) 16-34
complete
channel
development
host
module configuration register (TPUMCR) 19-11
service grant latch register (SGLR) 19-22
TPU interrupt configuration register (TICR) 19-14
bases 19-2
(TC) flag 15-54
interrupt enable (TCIE) 15-55
function select registers (CFSR) 19-15
interrupt
priority registers (CPR) 19-18
support control register (DSCR) 19-12
support status register (DSSR) 19-13
sequence registers (HSQR) 19-16
service request registers (HSSR) 19-17
19-21
,
14-36
enable register (CIER)
status register (CISR)
,
19-17
Freescale Semiconductor
19-5
19-5
,
,
19-19
19-15
,