MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 501
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
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13.4.5
The comparator is used during the approximation process to sense whether the digitally selected
arrangement of the DAC array produces a voltage level higher or lower than the sampled input. The
comparator output feeds into the SAR which accumulates the A/D conversion result sequentially,
beginning with the MSB.
13.4.6
The bias circuit is controlled by the STOP signal to power-up and power-down all the analog circuits.
13.4.7
The input of the successive approximation register (SAR) is connected to the comparator output. The SAR
sequentially receives the conversion value one bit at a time, starting with the MSB. After accumulating the
10 bits of the conversion result, the SAR data is transferred to the appropriate result location, where it may
be read from the IMB3 by user software.
13.4.8
The state machine receives the QCLK, RST, STOP, BYP, IST, CHAN[5:0], and START CONV signals,
from which it generates all timing to perform an A/D conversion. The start convert (START CONV) signal
indicates to the A/D converter that the desired channel has been sent to the MUX. IST indicates the desired
sample time. BYP indicates whether to bypass the sample amplifier. The end of conversion (EOC) signal,
notifies the queue control logic that a result is available for storage in the result RAM.
13.5
The digital control subsystem includes the control logic to sequence the conversion activity, the clock and
periodic/interval timer, control and status registers, the conversion command word table RAM, and the
result word table RAM.
The central element for control of the QADC64E conversions is the 64-entry CCW table. Each CCW
specifies the conversion of one input channel. Depending on the application, one or two queues can be
established in the CCW table. A queue is a scan sequence of one or more input channels. By using a pause
mechanism, sub-queues can be created in the two queues. Each queue can be operated using one of several
different scan modes. The scan modes for queue 1 and queue 2 are programmed in QACR1 and QACR2
(control registers 1 and 2). Once a queue has been started by a trigger event (any of the ways to cause the
QADC64E to begin executing the CCWs in a queue or sub-queue), the QADC64E performs a sequence
of conversions and places the results in the result word table.
Freescale Semiconductor
Digital Subsystem
Comparator
Bias
Successive Approximation Register
State Machine
MPC561/MPC563 Reference Manual, Rev. 1.2
QADC64E Legacy Mode Operation
13-37
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