MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 242

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

System Configuration and Protection
Figure 6-1
6-2
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•
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Periodic Interrupt Timer
timer to generate periodic interrupts for use with a real-time operating system or the application
software. The PIT provides a period from 1 µs to 4 seconds with a four-MHz crystal or 200 ns to
0.8 ms with a 20-MHz crystal. The PIT function can be disabled.
Software Watchdog Timer
asserts a reset or non-maskable interrupt, as selected by the system protection control register
(SYPCR), if the software fails to service the SWT for a designated period of time (e.g., because the
software is trapped in a loop or lost). After a system reset, this function is enabled with a maximum
time-out period and asserts a system reset if the time-out is reached. The SWT can be disabled or
its time-out period can be changed in the SYPCR. Once the SYPCR is written, it cannot be written
again until a system reset.
Freeze Support
SWT, PIT, TB, DEC, and RTC should continue to run during freeze mode.
Low Power Stop
timers are frozen but others are not.
shows a block diagram of the system configuration and protection logic.
(Section 6.1.11, “Freeze
(Section 6.1.12, “Low Power Stop
(Section 6.1.9, “Periodic Interrupt Timer
MPC561/MPC563 Reference Manual, Rev. 1.2
(Section 6.1.10, “Software Watchdog Timer
Operation”)—The SIU allows control of whether the
Operation”)—In low power modes, specific
(PIT)”)—The SIU provides a
(SWT)”)—The SWT
Freescale Semiconductor