MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 644

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Queued Serial Multi-Channel Module
compared. When a match occurs, the SPIF flag is set and the QSPI stops and clears SPE, unless
wraparound mode is enabled.
At reset, NEWQP is initialized to 0x0. When the QSPI is enabled, execution begins at queue address 0x0
unless another value has been written into NEWQP. ENDQP is initialized to 0x0 at reset but should be
changed to the last queue entry before the QSPI is enabled. NEWQP and ENDQP can be written at any
time. When NEWQP changes, the internal pointer value also changes. However, if NEWQP is written
while a transfer is in progress, the transfer is completed normally. Leaving NEWQP and ENDQP set to
0x0 transfers only the data in transmit RAM location 0x0.
15.6.4.1
The SPE bit in the SPCR1 enables or disables the QSPI submodule. Setting SPE causes the QSPI to begin
operation. If the QSPI is a master, setting SPE causes the QSPI to begin initiating serial transfers. If the
QSPI is a slave, the QSPI begins monitoring the PCS0/SS pin to respond to the external initialization of a
serial transfer.
When the QSPI is disabled, the CPU may use the QSPI RAM. When the QSPI is enabled, both the QSPI
and the CPU have access to the QSPI RAM. The CPU has both read and write access to all 160 bytes of
the QSPI RAM. The QSPI can read-only the transmit data segment and the command control segment and
can write-only the receive data segment of the QSPI RAM.
The QSPI turns itself off automatically when it is finished by clearing SPE. An error condition called mode
fault (MODF) also clears SPE. This error occurs when PCS0/SS is configured for input, the QSPI is a
system master (MSTR = 1), and PCS0/SS is driven low externally.
Setting the HALT bit in SPCR3 stops the QSPI on a queue boundary. The QSPI halts in a known state from
which it can later be restarted. When HALT is set, the QSPI finishes executing the current serial transfer
(up to 16 bits) and then halts. While halted, if the command control bit (CONT of the QSPI RAM) for the
last command was asserted, the QSPI continues driving the peripheral chip select pins with the value
designated by the last command before the halt. If CONT was cleared, the QSPI drives the peripheral
chip-select pins to the value in register PORTQS.
If HALT is set during the last command in the queue, the QSPI completes the last command, sets both
HALTA and SPIF, and clears SPE. If the last queue command has not been executed, asserting HALT does
not set SPIF or clear SPE. QSPI execution continues when the CPU clears HALT.
To stop the QSPI, assert the HALT bit in SPCR3, then wait until the HALTA bit in SPSR is set. SPE can
then be safely cleared, providing an orderly method of shutting down the QSPI quickly after the current
serial transfer is completed. The CPU can disable the QSPI immediately by clearing SPE. However, loss
of data from a current serial transfer may result and confuse an external SPI device.
15.6.4.2
The QSPI has three possible interrupt sources but only one interrupt vector. These sources are SPIF,
MODF, and HALTA. When the CPU responds to a QSPI interrupt, the interrupt cause must ascertained by
reading the SPSR. Any interrupt that was set may then be cleared by writing to SPSR with a zero in the bit
position corresponding to the interrupt source.
15-26
Enabling, Disabling, and Halting the SPI
QSPI Interrupts
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor