MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 374

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

External Bus Interface
9.5.7.3
BB assertion indicates that the current bus master is using the bus. New masters should not begin transfer
until this signal is negated. The bus owner should not relinquish or negate this signal until the transfer is
complete. To avoid contention on the BB line, the master should three-state this signal when it gets a
logical one value. This requires the connection of an external pull-up resistor to ensure that a master that
acquires the bus is able to recognize the BB line negated, regardless of how many cycles have passed since
the previous master relinquished the bus. Refer to
9-34
MPC500 Device
(Slave 1)
Bus Busy
Figure 9-25. Master Signals Basic Connection
MPC561/MPC563 Reference Manual, Rev. 1.2
External Bus
TS
BB
Figure
9-25.
Slave 2
Freescale Semiconductor
Master